1. Field of the Invention
The present invention relates to a fabricating method of a dynamic random access memory (DRAM) structure. In particular, the present invention is directed to a fabricating method of a DRAM structure integrated with a memory array region and a peripheral region.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is a critical element in many electronic products. There are a lot of memory cells in the DRAM to collectively form an array region to store data. Each memory cell is formed of a metal oxide semiconductor (MOS) and a capacitor electrically connected in series.
The capacitor is a data storage accessible to the drain of the MOS and electrically connected to the conductors in the storage node and the node contact to store data or to output data.
In order to decrease the time for fabrication and to simplify the fabrication process, the periphery circuits are fabricated collaterally. Further, in accordance with different demands of the elements, transistors of different functions are respectively formed in the memory array region and in the periphery circuit region. After the completion of the transistors, the interconnections are formed in accordance with different demands. However, with the trends of shrinking dimensions of the elements, a novel DRAM process is needed to increase the productivity and yield of DRAM.